The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method and device for manufacturing a capacitor structure in a dual damascene metal interconnect for integrated circuits. Merely by way of example, the invention has been applied to a copper dual damascene structure for advanced integrated circuit devices such as mixed signal devices. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to other types of metal layer such as tungsten, aluminum, and others.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. An example of a technique that allows for smaller feature sizes is called the dual damascene structure. Such damascene structure is often made of copper material for multilevel interconnect designs of conventional integrated circuit devices. High-speed microprocessors have used such damascene structure, as well as others.
The dual damascene structure includes a first copper metal layer and a second copper metal layer. Conventional copper structures are well known in the art. Although such structure has many benefits, there are still limitations. For example, such damascene structure includes copper material itself that migrates and causes problems with adjacent dielectric materials. Accordingly, barrier metal layers should often be used to maintain the copper from contact with dielectric materials. The damascene structure is also difficult to integrate with other device elements such as capacitors. An example of such a capacitor is a metal insulator metal capacitor, which is used for certain mixed signal integrated circuit devices. These and other limitations are described throughout the present specification and more particularly below.
From the above, it is seen that an improved technique for processing semiconductor devices including interconnect structures is desired.